When wiring formation of a semiconductor device is performed by a side wall wiring formation process, such as by forming a conformal metal film by chemical vapor deposition (CVD) on a core element, metal wiring line is formed on the side wall of the core. The wiring is then subjected to patterning and etchback on the entire surface thereof. However, the metal wiring line is sometimes damaged at the time of etchback, and the resistance of the wiring line can be undesirably increased.